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APPLICATION NOTE
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PROGRAMMING)
by Microcontroller Division Applications
1 INTRODUCTION
This application note is divided into two parts. The first part describes the ISP and FLASH programming specifications for the following ST7 devices: - ST72C104 - ST72C124 - ST72C171 - ST72C215 - ST72C216 - ST72C254 - ST72C314 - ST72C334 - ST72C411 (supports two ISP protocols, refer to the datasheet). The second part of this application note gives an example of how to use the ISP protocol to program the FLASH memory and the option bytes of a ST72C254, using another ST7 as a programming tool. 1.1 WHAT IS ISP? You can program any of the MCUs listed above by inserting it in the socket of a programming tool available from STMicroelectronics (EPB). You can also program them, using a serial interface, in In-Situ Programming (ISP) mode. The ISP feature allows you to update the content of Flash program memory when the chip is already plugged on the application board. ISP programming uses a serial protocol to interface a programming tool (which can be the EPB, or any other device that has the specifications described below).The ISP feature can be implemented with a minimum number of added components and board area impact. The ISP serial communication is based on a Master/Slave Architecture where the master is the ST7 to be programmed. So the clock speed depends on the speed of the ST7 CPU and this fact can produce some timing constraints.
AN1179/1199
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PROGRAMMING ST7 FLASH MICROCONTROLLERS IN ISP MODE
2 ISP SPECIFICATIONS
2.1 ISP HARDWARE DESCRIPTION In remote ISP mode, the ST7 has to be supplied with power (VDD and V SS) and an internal or external clock signal (you can use any of the oscillator configurations described in the datasheet). This mode needs five signals (plus the VDD signal if necessary) to be connected to the programming tool. These signals are: - RESET: device reset - VSS: device power supply ground - ISPCLK: ISP serial clock output - ISPDATA: ISP serial data input - ISPSEL: Remote ISP mode selection. This pin must be connected to VSS on the application board through a pull-down resistor. These pins are connected to the ST Programming tool using a HE10 type connector .
ISP mode used pin HE10 connector pin number ISPDATA 2 ISPCLK 4 ISPSEL 8 RESET 6 VSS 1,3,5 VDD 7
If any of these pins are used for other purposes in the application, a serial resistor can be implemented to avoid a conflict if the other device forces the signal level. Figure 1 shows a typical hardware interface to a standard ST7 programming tool. For more details on the pin locations, refer to the device pinout description of the ST7.
Figure 1. Typical Remote ISP Interface
sc O cl illa pti oc to on k r o al co r , c nf an a ig y n b ur u e at se io r n
XTAL
HE10 CONNECTOR TYPE TO PROGRAMMING TOOL 1
CL0
CL1
r to is es l r 11 na 4 io 72 pt T O rS fo
in te rn al o
OSC2
OSC1
VDD
ISPSEL
10K VSS RESET
ST7 FLASH
ISPCLK ISPDATA
l na io pt O
4.7K
APPLICATION
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PROGRAMMING ST7 FLASH MICROCONTROLLERS IN ISP MODE
2.2 ISP FUNCTIONAL DESCRIPTION The ISP mode is selected by a specific sequence on the ISPSEL pin. ISP is performed in three steps and makes use of the ST7's capability of executing RAM-resident code: - Selection of ISP mode - Download code in RAM - Execution of the downloaded code in RAM to program the user program into the FLASH The programming sequence using the ISP protocol is described in Figure 2.
Figure 2. Flowchart of the ISP Protocol .
Put the ST7 in ISP mode
33 Rising edges on ISPSEL after reset pin is released (rising edge on RESET pin) while ISPDATA pin stays low
ST7 is in ISP mode
A bootrom, in the ST7, is executed in order to read (through the ISPDATA pin) and load the `boot-strap' program into RAM. Then the ST7 jumps to the RAM to execute the `boot-strap'
ST7 Execute the `bootstrap' program in RAM
The `boot-strap' program reads data through the serial link and programs the Flash memory and the option byte.
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2.2.1 ISP MODE SELECTION To enter ISP mode the ST7 needs to be powered-on and connected to an available clock system (internal RC, external RC, external clock or Crystal/resonator). The factory configuration is internal RC (for clock selection refer to the datasheet). During the reset phase, a sequence on the ISPSEL pin is used to enter ISP mode. ISPDATA must be tied low until the first rising edge of ISPCLK. The sequence is shown in Figure 3.
Figure 3. ISP mode selection
RESET
ISPDATA
ISPCLK
ISPSEL 33 Rising Edges In a window of 256 CPU cycles Reset Phase: 4096 CPU cycles ISP Bootrom execution
Note: The 33 pulses do not need to be synchronized with the CPU clock. In this mode, the reset phase is still 4096 CPU cycles.
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2.2.2 DOWNLOADING CODE IN RAM At the end of the Reset phase, the reset vector is fetched into the ISP bootrom. The bootrom code is executed, to configure the port logic and to receive data serially through the ISPDATA pin to be stored in the RAM area. To execute this ISP boot program, the status of the ISPDATA pin must externally forced LOW just after the RESET phase, until the first rising edge of ISPCLK. Downloading the code in the RAM area is done sequentially from the least significant address of the RAM. The number of bytes to be downloaded (after the first one) is specified in the first data byte transfer and so can not exceed 255 bytes. The ISP bootrom program and ISP protocol flowchart are shown in Figure 4.
Figure 4. ISP Bootrom: Code & Flowchart Enter with Valid ISPDATA .ISP_bootrom BSET BSET BSET CLR BRES .nbyte CLR LD .nbit BSET BTJF .read RLC BRES DEC JRNE TNZ JRNE LD INC JP
.incy
PxDR,#ISPCLK PxDDR,#ISPCLK PxOR,#ISPCLK Y PxDR,#ISPCLK A ;A=ReceivedData X,#$08 ;X=BitCounter PxDR,#ISPCLK PxDR,#ISPDATA,read ;Update the carry flag A PxDR,#ISPCLK X nbit Y store RAMBEG,A ;RAMBEG=NB_byte Y nbyte (RAMBEG,Y),A Y,RAMBEG incy {RAMBEG + 1}
X=8
Force ISPCLK line High Copy ISPDATA to carry Flag
Rotate A Register
c 7 0
Force ISPCLK line Low X=X-1
.store LD CP JRNE .end JP
No
X=0 Yes Store byte
A complete timing diagram is shown in Figure 5 and Figure 6Figure 6.
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Figure 5. ISP bit communication
RESET
4096 CPU CYCLES
N CPU CYCLES
12 CPU CYCLES
13 CPU CYCLES
fCPU READ DATA ISPCLK
ISPDATA
INITIALIZATION PHASE
DATA BIT
DATA BIT
ISP MODE SELECTION
BOOTROM EXECUTION
Note: The initialization phase duration is device dependent, timings are given in Section 2.2.3.4
Figure 6. ISP byte communication
ISPCLK
ISPDATA
BYTE NB
BYTE 1
BYTE 2
BYTE NB-1
BYTE NB
BOOTROM EXECUTION
USER RAM PROGRAM EXECUTION
2.2.3 EXECUTING CODE IN RAM, FLASH PROGRAMMING After downloading the program in RAM, jumping to the start address of this program starts the FLASH programming operation. The FLASH program memory is organised as a single 8-bit wide memory block which can be used for storing both code and data constants. The FLASH program memory is mapped in the upper part of the ST7 addressing space and includes the reset and user interrupt vector area.
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2.2.3.1 Programming the FLASH The FLASH area is driven by the Flash Control & Status Register (EEXCSR). The FLASH area can program up to 16 bytes in the same erase & programming cycle.The FLASH is mono-voltage, a charge pump generates the high voltage internally to enable the erase and programming cycles. The global programming cycle duration is controlled by an internal circuit. Flash Control & Status (EEXCSR) Register description
Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 OPT LAT 0 PGM
- Bit 7:3 = Reserved, forced by hardware to 0. - Bit 2 = OPT Option byte access Option byte enable at high level. It allows read and write access to the option bytes in ISP mode. The two option bytes are selected by their own address (see table below). 0: User FLASH program area selected 1: Option Bytes area selected - Bit 1 = LAT Latch Access Transfer This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if the PGM bit is cleared. 0: Transfer latches not accessible 1: Transfer latches accessible - Bit 0 = PGM Programming control and status This bit turns on the charge-pump. This bit must be set to start the programming cycle. At the end of the programming cycle, this bit is automatically cleared, stopping the charge pump. 0: Programming finished or not yet started 1: Programming cycle is in progress The EEXCSR address and the option byte addresses are device dependent and summarized in the following table:
ST7 FLASH ST72C104 ST72C124 ST72C171 ST72C215 ST72C216 ST72C254 ST72C314 ST72C334 ST72C411 EEXCSR Option Byte 1 Option Byte 2 0026h E000h E001h 002Dh C000 C001 0026h E000h E001h 0026h E000h E001h 0026h E000h E001h 0026h E000h E001h 002Dh C000 C001 002Dh C000 C001 0026h F000 -
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Read Operation (LAT=0) The FLASH can be read as a normal ROM location when the LAT bit of the EEXCSR register is cleared. Write Operation (LAT=1) To access the write mode, the LAT bit has to be set by software (the PGM bit remains cleared). When a write access to the FLASH area occurs, the 8-bit data bus is memorized in one of the 16 8-bit data latches. The data latches are selected by the lower part of the address (A<3:0> bits). When the PGM bit is set by software, all the previous bytes written in the data latches (up to 16) since the last programming, are programmed in the FLASH cells. The effective high address (A<15:4> bits) is determined by the last FLASH write sequence. If 16 consecutive write instructions are executed by sweeping from A<3:0>=0h to A<3:0>=Fh, with the same higher part of the address (A<15:4> bits), the 16 data latches will be written in the same row of the FLASH matrix. At the end of the programming cycle, the LAT bit is automatically reset, and the 16 data latches are cleared. To avoid wrong programming, the user must take care that all the bytes written between 2 programming sequences have the same high address: only the four Least Significant Bits of the address can change. Note: If only N (N<17) write instructions are executed before the PGM bit is set, only the N bytes of the matrix will be written.
Figure 7. FLASH Programming Flowchart READ MODE LAT=0 PGM=0 WRITE MODE LAT=1, PGM=0 WRITE UP TO 16 BYTES IN FLASH LATCH (with the same 12 MSB of the address) START PROGRAMING CYCLE LAT=1, PGM=1 WAIT FOR END OF PROGRAMMING LAT=0 ,PGM=0 (reset by Hardware)
READ BYTES IN FLASH AREA
Note: If a programming cycle is interrupted (by software/RESET action), the data integrity in memory will not be guaranteed.
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Figure 8. FLASH Programming Cycle
READ OPERATION NOT POSSIBLE READ OPERATION POSSIBLE
BYTE 1
BYTE 2
BYTE 16
PROGRAMMING
WRITING DATA LATCHES
tPROG
LAT BIT
PGM BIT
2.2.3.2 Programming the option bytes Some ST7 devices have Option Bytes for configuring the device features. The Option Bytes can be only accessed in ISP mode, they can be programmed by writing the corresponding byte (byte row is included inside FLASH Matrix and can be managed as a normal FLASH row). For more details refer to FLASH Control and Status register description. In ROM devices the Option Bytes are fixed in hardware by the ROM code. The following is an example algorithm for programming devices with up to two option bytes using the standard ISP protocol.
Figure 9. Option Bytes Programming Code & Flowchart
NBCOL BYTE $2 CLR BRES CLR LD BSET BTJF RLC BRES DEC JRNE BSET BSET LD INC CP JRNE BSET BTJT BRES ;2 option bytes Y PxDR,#ISPCLK A ;A=ReceivedData X,#$08;X=BitCounter PxDR,#ISPCLK PxDR,#ISPDATA,read A PxDR,#ISPCLK X nbit EEXCSR,#OPT EEXCSR,#LAT EEPBEG,Y),A Y Y, NBCOL .nbyte EEXCSR,#PGM EEXCSR,#LAT,* EEXCSR,#OPT
WRITE MODE OPT=1,LAT=1, PGM=0
.nbyte .nbit .read
WRITE the 2 OPTION BYTES IN FLASH LATCH
@Option byte 1 Address @Option byte 2 Address
START PROGRAMMING CYCLE OPT=1,LAT=1, PGM=1
WAIT FOR END OF PROGRAMMING
.store .end
LAT=0 ,PGM=0 (reset by Hardware) OPT=0 (reset by Software)
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2.2.3.3 Bootstrap Program content Depending on the downloaded bootstrap program in RAM, the memory programming can be completely customized (number of bytes to program, location of the program, programming of option bytes, or selecting any other serial communication interface for downloading). You can also use the bootstrap program to run a test program in RAM even if you are using a ROM device. The example given in the second part contains a bootstrap program able to program 8 Kbytes of FLASH and the option bytes of the ST72254 reading in the data to be programmed through the I/O port. In most ST7 devices, you can also use the SPI protocol to read in the data to be programmed in the FLASH. Refer to the SPI protocol example given later in this document. Whatever the selected protocol, the bootstrap program will always execute the same algorithm shown in Figure 10.
Figure 10. Bootstrap program algorithm.
READ 16 bytes through ISPDATA pin
PROGRAM the previous 16 bytes in the FLASH
NO
TEST if the number of bytes to program is reached YES Infinite loop WAIT for a reset to start the execution of the new FLASH content
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SPI protocol: To use this protocol, the SPI has to be configured as follows: - The SS pin should be configured in Master mode. - The SPI Master output (MOSI) pin should be disabled. For more details refer to the SPI chapter of the datasheet and the Miscellaneous Register (where available). The following is a bootstrap code example for programming the FLASH using the SPI protocol.
COUNT BYTE number NBCOL BYTE $10 LD LD LD LD CLR .main LD .rbyte BTJF LD BSET LD INC CP JRNE CALL .loop CP JRNE BTJF CALL .end BRES .store BSET BTJT LD ADD LD RET .spi ;byte_number ;number of latch A,#$0B ;pinNSS soft MSCR2,A;set SMOD bit A,#$5C SPICR,A;SPI Y SPDAT,X SPSR,#SPIF,rbyte A,SPDAT EEXCSR,#LAT (EEPBEG,Y),A Y Y,NBCOL loop store Y, COUNT rbyte EEXCSR,#LAT,end store SPCR,#SPE ; stop spi EEXCSR,#PGM EEXCSR,#LAT,* A,NBCOL A,#$10 NBCOL,A
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2.2.3.4 ISP Programming Time The time required to program the FLASH using the ISP protocol can be estimated using the following table:
Table 1. ISP programming time evaluation table ISP mode selection/ reset Downloading code in RAM Bootrom Execution 25 * 8 *N byteR * TCPU + Tinit FLASH Programming Bootstrap Execution Data Transfer I/O Protocol 8 * 25 * TCPU* NbyteF SPI Protocol 4 * TCPU* NbyteF Flash Programming
4096 * TCPU
Tprog* N byteF /16
Where: TCPU is the CPU period in seconds (down to 0.125s), NbyteR is the number of bytes able to be downloaded in RAM (up to 255) NbyteF is the number of bytes to be programmed in FLASH (up to 16 Kbytes i.e. 16386) Tprog is the Typical Flash erase and program cycle (8ms) Tinit is the time between the end of the reset phase and the first rising edge on ISPCLK. Tinit is device dependent)
Table 2. Initialization time (Tinit) according the ST7. ST7 FLASH ST72C104 ST72C124 ST72C171 ST72C215 ST72C216 ST72C254 ST72C314 ST72C334 ST72C411 Tinit (CPU clock) 45 45 45 45 45 45 45 45
1602 ISPSC 1609 ISPN
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3 ST72C254 ISP PROGRAMMING EXAMPLE
3.1 APPLICATION EXAMPLE The example described here shows how to program the ST72C254 using ISP. The downloading is done from another ST72C254 (acting as a programming tool). The boot-strap program described in this document, programs the FLASH and the Option bytes of the ST72254 using the ISP protocol (not the SPI protocol).
Figure 11. Application Circuit
LED (light ON when download complete)
PB7
PB0 PB1 PB2 PB3 ST72C254
RESET ISPCLK ISPDATA ISPSEL ST72C254 APPLICATION BOARD
PROGRAMMING TOOL
In this example, there is no external clock on the application board because the ST72C254 is configured to use its internal oscillator: a 4 MHz RC oscillator (TCPU=250ns). As shown in Section 2.2, ISP is performed in three steps: - Select ISP mode - Download code in RAM - Execute code in RAM 3.1.1 Select ISP mode Entering ISP mode is done by generating 33 pulses on the ISPSEL pin during the reset phase (window of 256 cycles).
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PROGRAMMING ST7 FLASH MICROCONTROLLERS IN ISP MODE
3.1.2 Downloading code in RAM After selecting ISP mode, the ST72C254 fetches the reset vector into a common bootrom. The bootrom which is then executed, receives data serially through the ISPDATA pin and stores it in the RAM area. Downloading the code in RAM is done sequentially from the lsb address of the RAM (0x0080 in the ST72254). The number of bytes to be downloaded is specified in the first byte transfer (and stored in address 0x0080 of the RAM). The number of downloaded bytes can not exceed 255. The transmission speed is controlled by the ST72C254 by generating ISPCLOCK. The PB1 pin of the programming tool is configured as input with pull-up in order to tie the ISPCLK line high until the ISPCLK drives the line. When the ST72C254 is ready to read the first bit, it generate a low transition on ISPCLK. The programming tool sends the first bit. The ST72C254 generate a high transition and stores this bit. 3.1.3 Executing code in RAM After downloading the code in RAM, the downloaded program (boot-strap program) is executed. Depending on the downloaded program in RAM, the memory programming can be completely customized. In this example, the bootstrap program is written to read 8 Kbytes through the ISPDATA pin (using the I/O protocol) and program them in the FLASH. The Bootstrap also programs the 2 option bytes with a predefined value. The bootstrap code located in the file `bootstra.asm' is located in ROM at the address E000hE0FFh. This code will be executed in the RAM of the ST72C254 to be programmed, so the absolute label value will be wrong. To get around this, you can use the following directives.
segment byte at 81-14F 'ramexe254' segment 'ramexe254 > rom_boot'
The code following these directives will be place in the segment `rom_boot' but it will be linked to be executed in the segment `ramexe254'.
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3.2 CODE & FLOWCHART 3.2.1 Programming tool flowchart
START Init I/O Port Reset ST72C254 and send 33 rising edges
Read `boot' program (stored in E000-E0FF) and send it to ST72C254
Read ` prog' data: 256 bytes to send: store in E100-E1FF and send it 32 times to ST72C254 32*256=8Kbyte
Switch on download LED STOP
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3.2.2 Programming tool code
ST7/ ;************************************************************************ ; TITLE LOAD_ISP.ASM ; AUTHOR ST7 Application Group ; DESCRIPTION Program ST72254 in ISP mode ; Note: THIS FILE MUST BE LINKED BEFORE BOOTSTRA.ASM ;************************************************************************ TITLE "LOAD_ISP.ASM"
#INCLUDE "ST72254.INC" #define #define NB_BYTEEQU BYTES segment 'ram0' PTR DS.B ISPDATA ISPCLK $FF 2 1 ; Number of bytes loaded in RAM of ST72254
1
WORDS segment byte 'rom_boot' .boot DC.B {NB_BYTE-1} ; The address 'boot' must be place at the first address of the ; segment 'rom_boot'. So this file must be linked before the ;file 'bootstra.obj' which uses also the segment 'rom_boot' ;************************************************************************ ; MAIN PROGRAM ; ============ ; ;************************************************************************ segment 'rom3' .main LD LD LD LD LD LD BRES A,#32 ; Init PTR to 32, In this example, 256 bytes PTR,A ; will be send 32 times (256 * 32 = 8 Kbytes) A,#%10001101 ; \ PB7 -> OUT -> Operation OK PBDDR,A ; | PB3 -> OUT -> Conn to ISPSEL of ST72254 A,#%10001111 ; | PB2 -> OUT -> Conn to ISPDATA of ST72254 PBOR,A ; / PB1 -> IN Pull-Up -> Conn to ISPCLK of ST72254 PBDR,#ISPDATA ;PB0 -> OUT -> Conn to RESET of ST72254
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CALL LD BSET edges BSET BRES DEC JRNE CALL CALL BSET end_f JP
tempo ; X,#33 ; \ 33 Pulses to enter ISP mode PBDR,#0 ; | RESET = 1 PBDR,#3 ; | ISPSEL = 1 PBDR,#3 ; | ISPSEL = 0 x ; | 16*33 = 528 cycles edges ;/ send_prog_in_ram send_prog_in_eeprom PBDR,#7 ; Inform that Programming is complete end_f ; Infinite loop
;************************************************************************ ; TEMPO PROGRAM ; ============= ; ;************************************************************************ .tempo LD tp DEC JRNE ret A,#$80 A tp
;************************************************************************ ; SEND 1 BYTE ROUTINE ; =================== ; ;************************************************************************ .send_1_byte LD trans1 BTJT RLC JRC emi0 BRES JRA emi1 BSET trans2 BTJF DEC JRNE RET
X,#$08 ; Receive 8 bits PBDR,#ISPCLK,trans1 ; low transition A ; A.0 put in carry emi1 ; PBDR,#ISPDATA; Data = 0 trans2 ; PBDR,#ISPDATA; Data = 1 PBDR,#ISPCLK,trans2 ; high transition X ; decrement counter trans1 ; All bits sent ?
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;************************************************************************ ; SEND PROG IN ST72254 RAM ; ======================== ;************************************************************************ .send_prog_in_ram CLR Y ; Clear Y data LD A,(boot,Y) ; Read BOOT_PROG at adr 80h of 254 CALL send_1_byte ; Send each byte INC Y ; CP Y,#NB_BYTE ; All bytes sent JRNE data ; If not, continue RET
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;************************************************************************ ; SEND PROG IN ST72254 EEPROM ROUTINE ; =================================== ;;************************************************************************ .send_prog_in_eeprom ; data2 CLR Y ; Reset pointer data1 LD A,(prog,Y) ; Read byte to send CALL send_1_byte ; Send byte INC Y ; Go to the next byte CP Y,#$00 ; 256 bytes sent ? JRNE data1 ; If not, continue DEC PTR ; Else, Dec PTR, send 256 bytes JRNE data2 ; All 8 Kbytes loaded ? If not, continue RET ;*************************************************************************** ; ; CODE THAT WILL BE PUT IN EEPROM OF THE ST72254 ; ;*************************************************************************** * segment 'rom2' .prog DC.B DC.B DC.B DC.B DC.B DC.B DC.B DC.B DC.B DC.B DC.B DC.B DC.B DC.B DC.B DC.B $20,$20,$20,$53,$54,$37,$20,$4D,$69,$63,$72,$6F,$73,$20,$20,$20 $46,$4C,$41,$53,$48,$20,$50,$52,$4F,$47,$52,$41,$4D,$49,$4E,$47 $20,$20,$20,$53,$54,$37,$20,$4D,$69,$63,$72,$6F,$73,$20,$20,$20 $46,$4C,$41,$53,$48,$20,$50,$52,$4F,$47,$52,$41,$4D,$49,$4E,$47 $20,$20,$20,$53,$54,$37,$20,$4D,$69,$63,$72,$6F,$73,$20,$20,$20 $46,$4C,$41,$53,$48,$20,$50,$52,$4F,$47,$52,$41,$4D,$49,$4E,$47 $20,$20,$20,$53,$54,$37,$20,$4D,$69,$63,$72,$6F,$73,$20,$20,$20 $46,$4C,$41,$53,$48,$20,$50,$52,$4F,$47,$52,$41,$4D,$49,$4E,$47 $20,$20,$20,$53,$54,$37,$20,$4D,$69,$63,$72,$6F,$73,$20,$20,$20 $46,$4C,$41,$53,$48,$20,$50,$52,$4F,$47,$52,$41,$4D,$49,$4E,$47 $20,$20,$20,$53,$54,$37,$20,$4D,$69,$63,$72,$6F,$73,$20,$20,$20 $46,$4C,$41,$53,$48,$20,$50,$52,$4F,$47,$52,$41,$4D,$49,$4E,$47 $20,$20,$20,$53,$54,$37,$20,$4D,$69,$63,$72,$6F,$73,$20,$20,$20 $46,$4C,$41,$53,$48,$20,$50,$52,$4F,$47,$52,$41,$4D,$49,$4E,$47 $20,$20,$20,$53,$54,$37,$20,$4D,$69,$63,$72,$6F,$73,$20,$20,$20 $46,$4C,$41,$53,$48,$20,$50,$52,$4F,$47,$52,$41,$4D,$49,$4E,$47
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3.2.3 Bootstrap program flowchart
START Init I/O Port Init FLASH Control register Store bytes read on ISPDATA Start at HIGHAD
NO
16 bytes received YES
Program 16 bytes in FLASH
NO
256 bytes received YES
Increment High Byte of HIGHAD
NO
8 Kbytes received
YES STOP
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3.2.4 Bootstrap program code
ST7/ ;*************************************************************************** ; TITLE BOOTSTRA.ASM ; AUTHOR ST7 Application Group ; DESCRIPTION Bootstrap loaded Program used by ISP programming ; ; PB5 = ISPDATA ; PB6 = ISPCLOCK ; ; ***** CHANGE LOADED ADRESS ***** ; - Change start address in (1) ; - Change low part of the address in (2) and in (4) ; - Change High part of the address in (3) ; ; ***** Change OPTION BYTE ***** ; - Change Option byte 1 in (5) ; - Change Option byte 2 in (6) ; ;*************************************************************************** TITLE "LOAD_ISP.ASM" ; #INCLUDE "ST72254.INC" segment byte at 81-14F 'ramexe254' segment 'ramexe254>rom_boot' ; the following code is located in the segment 'rom_boot' ; but all the labels are calculated to be placed BYTES ; in the RAM of the ST72254 starting at the address 80h. ; Boot code program start at 81h. ; 1st byte at 80h-> Nb of bytes .HIGHADDC.W $E000 ; (1) Adr where prog will be load in FLASH .LOWAD DC.B $00 ; (2) Copy of the low part of the address .IDCODEDC.B $02 ; Not use in this version .COUNT DC.B $00 ; Variable COUNT WORDS ;************************************************************************ ; MAIN PROGRAM OF THE BOOT ; ======================== ; ;************************************************************************
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.begin RSP LD LD LD BRES LD AND CALLR CALLR inf_loop JRA A,#$40 PBDDR,A PBOR,A PBDR,#6 A,EEXCSR A,#$F8 eep_prg ob_prg inf_loop ; ; ; ; ; ; ; ; \ PB6 (SCK) is output | / ISPCLOCK = 0 read continuously Mask reserved bit Program FLASH Program Option Byte
; Infinite loop
;************************************************************************ ; OPTION BYTE LOADED PROGRAM ; ========================== ; ;************************************************************************ .ob_prg LD LD LD LD BSET BSET OB_1 LD LD INC OB_2 LD LD CALLR BRES RET
A,#$E0 ; (3) High part ----> CHANGE HERE HIGHAD,A ; X,#$00 ; (4) Low part -----> CHANGE HERE {HIGHAD+1},X EEXCSR,#2 ; OPT=1 EEXCSR,#1 ; LAT=1 A,#$FC ; (5) OB_1 ---------> CHANGE HERE ([HIGHAD.w],X),A; Store OB_1 X ; Go to the second OB A,#$6D ; (6) OB_2 ---------> CHANGE HERE ([HIGHAD.w],X),A ; Store OB_2 flashp EEXCSR,#2 ; OPT=0
;************************************************************************ ; FLASH LOADED PROGRAM ; ===================== ;************************************************************************ .eep_prg LD A,#$0F ; \ Program FLASH 16 by 16 LD COUNT,A ;/ start BSET EEXCSR,#1 ; Write data latches E2LAT=1 BRES EEXCSR,#0 ; Program data latches PGM=0 n_data CALLR read_data ; Program data
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LD CP JRNE JRA suit0 INC JRNE suit1 INC CALLR LD ADD LD CP JRNE LD LD INC LD CP JREQ JRA end_eepRET
([HIGHAD.w],X),A ; Write to FLASH the latched data X,COUNT ; 16 bytes stored ? suit0 ; If not -> go to suit0 suit1 ; Else -> go to suit1 X ; Go to next address n_data ; and program it X ;\ flashp ; | Program the 16latched datas in FLASH A,COUNT ; | Re-init COUNT A,#$10 ; | and go to the next address COUNT,A ;/ X,#00 ; Verify if 256 bytes send start ; If not, continue (jump to start) A,#$0F ;\ COUNT,A ; | If yes, re-init COUNT HIGHAD ; | Increment High part of address A,HIGHAD ; | Verify if address FFFFh was prog A,#00 ; | and if yes ---> exit end_eep ;/ start ;
;************************************************************************ ; FLASH 16 DATAS WRITE PROGRAM ; ============================= ;************************************************************************ .flashp BSET waitprg BTJT BRES RET
EEXCSR,#0
; Program data latches PGM=1
EEXCSR,#1,waitprg ; Wait end of prog E2LAT =0 EEXCSR,#0 ; Program data latches PGM=0
;************************************************************************ ; RECEIVE 1 BYTE PROGRAM ; ====================== ;************************************************************************ .read_data BRES CLR LD n_bit BSET
PBDR,#6 A Y,#$08 PBDR,#6
; ISPCLOCK = 0 ; ; Will receive 8 bits ; ; ISPCLOCK = 1
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PROGRAMMING ST7 FLASH MICROCONTROLLERS IN ISP MODE
read
fin
BTJF RLC BRES DEC JREQ JRA RET
PBDR,#5,read A PBDR,#6 Y fin n_bit
; ; ; ; ; ;
read a bit of ISPDATA Put read bit in LSB of A ISPCLOCK = 0 Decrement counter If 8 bits receive -> exit If not, continue
END
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PROGRAMMING ST7 FLASH MICROCONTROLLERS IN ISP MODE
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